The high-density integration of semiconductor devices have been continued with the development of the semiconductor industries for several decades. Therefore, metal lines delivering electrical signals are also demanded for scaling down of the width to a few nm and several issues that have not been appeared begin to occur. For example, an increased electric field between metal lines according to the decreases of interconnection pitches, a degradation of mechanical stabilities of dielectrics between the metal lines due to the uses of the low-k dielectrics to reduce parasitic resistance, and an line edge roughness (LER) resulting from the formation of nanoscale patterns. These problems cause the reliability issues of the interconnections.
Moreover, current devices for mass productions are operating under unipolar or bipolar pulse conditions, but previous methods for reliability analysis were developed under DC bias conditions, which makes it difficult to predict accurate lifetimes of the practical devices.
In addition, a soft breakdown (SBD) and hard breakdown have occurred and studied in terms of gate insulators. Recently, as the low-k dielectrics employs and operating voltages decreases, effects on the lifetime of the dielectrics between metal lines are increasing, which motivate researchers to study the SBD in the interconnections.
SBD: Effect of low-field and low-k materials
Therefore, we are focusing on two areas to solve the newly occurred reliability problems according to the scaling of the interconnection. First, studying the time-dependent dielectric breakdown (TDDB) and electromigration (EM) tests, which are typical methods for reliability measurements, under diverse pulse conditions. Second, phenomena related with the SBDs such as noisy leakage current and successive breakdowns. The ongoing researches including figures are shown as follows.
Time-dependent dielectric breakdown: Effect of pulsed electric field
Electromigration: Structural effects for memory devices