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서울대학교 미세유연소자재료 연구실SNU Nano Flexible Device Materials Lab

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Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits

Home Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits

Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits

저자

S.-H. Hwang, B.-J. Kim, H.-Y. Lee, and Y.-C. Joo

저널 정보

J. Elect. Mat., 41(2) pp. 232-240 (2012)

출간연도

2012

링크

https://doi.org/10.1007/s11664-011-1767-x

S.-H. Hwang, B.-J. Kim, H.-Y. Lee, and Y.-C. Joo, “Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits”, J. Elect. Mat., 41(2) pp. 232-240 (2012)